One Rack, a Thousand Agents
Picture a data centre floor at midnight. Row after row of racks hum under cold white light, and somewhere in that forest of steel, a single machine is quietly doing the work that used to take a whole room.
On November 10, AMD unveiled its 6th Gen EPYC server processors, codenamed Venice, at a launch event in Las Vegas. The new AMD EPYC 6 Venice lineup is built on the company’s Zen 6 architecture and manufactured on TSMC’s two-nanometre process, and it arrives with one job in mind: powering the age of AI agents.
It is the most ambitious server chip AMD has ever shipped. The flagship packs 256 cores into a single socket, and AMD says it can run several times more AI agents per watt than the competition. But as with every big chip launch, the headline numbers only tell half the story.
What AMD Actually Launched
The EPYC 6 family starts with ten processors, split into two groups. One group chases raw density, with the most cores AMD has ever put in a socket. The other chases speed, with fewer cores running at much higher clock rates.
At the top of the density group sits the EPYC 9996. It carries 256 Zen 6 cores and 512 threads per socket, with a full gigabyte of L3 cache and a 600-watt power envelope. Put two of them in one server and you get 512 cores and 1,024 threads in a single box.
The frequency group is led by chips like the EPYC 9686F. These parts have 96 cores, a base clock of 4.05 gigahertz and a boost clock reaching 5.3 gigahertz. They are aimed at workloads where each core needs to move fast.
Every chip in the family is built on TSMC’s N2P process, the two-nanometre node that also sits at the heart of the AI industry’s biggest bets. That connection matters: TSMC recently committed a billion dollars to Anthropic and OpenAI, and its newest process is now the foundation of AMD’s server push too.
Why AMD Is Betting on AI Agents
For years, server processors were judged on how well they served databases, websites and virtual machines. AMD is now arguing that the next great workload is different: fleets of AI agents that plan, call tools, run code and check each other’s work around the clock.
Agents are hungry in a particular way. A single agent session might spin up a sandbox, run a code interpreter, query a database and draft a report — all at once. Multiply that by thousands of users, and the CPU becomes the traffic controller for the whole operation.
That is the pitch behind Venice. AMD says the chips are designed for agent orchestration, running many agents in parallel sandboxes, and handling the tool calls and data movement that sit around the GPU. Its “In Depth” event framed Venice around agentic AI and a new memory technology called MEXT.
The timing is no accident. AI labs are racing to put agents inside every product, and Google’s new TPU chips show that every major player is rebuilding its hardware for the same shift. AMD wants a piece of the infrastructure underneath it all.
The Numbers AMD Wants You to See
AMD came to Las Vegas with bold claims. The company says the flagship EPYC 9996 delivers up to 3.7 times the performance of Nvidia’s Vera CPU, the Arm-based processor at the centre of Nvidia’s own server platform.
It also claims up to 3.3 times more agents per watt than Vera, and roughly 2.2 times the performance of Intel’s Xeon 6980P in the same class of work. On top of that, AMD quotes a 27 percent uplift in instructions per clock over its previous Zen 5 architecture.
Those are vendor numbers, and they should be read as such. AMD’s comparisons use its own chosen workloads and configurations, and no independent lab has yet repeated them end to end. Still, the direction is clear: AMD is measuring itself against Nvidia’s CPU, not just Intel’s.
That framing is a statement in itself. A decade ago, AMD’s server rival was Intel alone. Today, the company that makes the world’s most wanted AI accelerators is also the benchmark AMD has to beat — even though Nvidia’s own week has been turbulent, with its shares sliding on lawsuit news.
The First Independent Tests Tell a Messier Story
Early independent testing, published on launch day, gives the 9996 a more complicated report card. In one widely watched test, a dual-socket system with two 9996 chips scored about 93 percent higher than a dual-socket system using the previous flagship, the 192-core EPYC 9965, in an unofficial SPEC CPU 2026 integer-rate estimate.
But the same round of testing found the 256-core newcomer slower than its 192-core predecessor in a database benchmark. That surprises people who equate more cores with more speed — and it is a reminder that database work rewards fast individual cores as much as raw parallelism.
Neither result settles the question. One benchmark measures raw throughput across many threads; the other measures how quickly a system answers a stream of small, latency-sensitive queries. Real data centres run both kinds of work, and often on the same machine.
What the early numbers do show is that Venice is not a simple, across-the-board upgrade. Its advantage is biggest where work splits cleanly across hundreds of cores — exactly the kind of parallel agent workloads AMD is targeting.
What It Costs and When You Can Buy It
AMD did not announce official pricing at the launch, but its price list, which surfaced in late September, puts the flagship EPYC 9996 at $14,904 in quantities of a thousand. That figure may change, and AMD gave no volume or lead-time figures on Tuesday.
Servers built on the new chips are already shipping from major data centre suppliers, according to AMD, and partners including Lenovo, Hyve Solutions and Cornelis were named at the event. Hyve is offering the processors in rack-scale systems built on its Axis platform.
Cloud availability is coming, but not instant. Microsoft Azure is preparing instances powered by the new chips, with its HDv2 offering in preview for AI data processing and high-performance computing. Oracle Cloud Infrastructure is planning E7 instances for enterprise applications, with no firm dates given for either.
One detail buyers should note: Venice uses a new SP7 socket, which is not backward compatible with the SP5 socket used by the previous generation. Upgrading means new boards, not just a chip swap — a real cost for data centres that were hoping for a drop-in replacement.
What Comes Next for the Venice Platform
AMD’s roadmap stretches well past this launch. Early next year, the SP8 platform arrives with processors spanning 8 to 128 cores, with reports of 22 models starting at around $700 for the first half of 2027.
Later in 2027 comes Venice-X, which adds 3D V-Cache to the design. The top Venice-X part is expected to pair 96 cores with 1,152 megabytes of L3 cache. Consumer processors based on Zen 6, codenamed Olympic Ridge, are expected next year but have not been announced.
Further out, Verano variants with LPDDR5X memory are expected in the second half of 2027. AMD is clearly treating Venice as a platform, not a single launch — a family that will grow across sockets, caches and memory types over the next eighteen months.
What the EPYC 6 Launch Really Means
Strip away the benchmark charts and the launch is about a shift in what a server CPU is for. AMD is no longer selling a general-purpose workhorse and hoping AI workloads happen to fit. It is designing chips for a world where thousands of agents run side by side.
Whether Venice wins that world depends on the tests that come next. The early numbers say it is a formidable throughput machine with real caveats in latency-sensitive work. The cloud rollouts, the pricing and the independent reviews over the coming weeks will decide how much of AMD’s story holds up.
For now, one thing is certain: the race to power AI agents is no longer a GPU-only contest. The CPU is back at the centre of the argument — and AMD just put 256 cores behind its case, according to SiliconANGLE.
